This invention relates to a signal processor for use in carrying out real-time digital signal processing, such as fast Fourier transform. The signal processor can be used as a digital filter.
In general, the real-time digital signal processing can accomplish a high reliability and a high stability in comparison with analog signal processing and realizes a filter and a modem which have a high reliability and a high stability. In addition, the real-time digital signal processing enables a time-varying adaptive filter which can not be expected in the analog signal processing.
However, the real-time digital signal processing is disadvantageous in that it is necessary to carry out a great deal of computation. More specifically, an analog input signal is sampled into samples. Each sample is converted into sampled digital data. The real-time digital processing must be carried out for the sampled digital data during every sampling interval. By way of example, let a fourth-order recursive digital filter be used in processing a telephonic audio signal at sampling rate of 8 kHz. In the fourth-order recursive filter, multiplications and additions must be executed eight times during every sampling interval of 125 microseconds. In the meanwhile, a filter according to analog technique inevitably comprises analog circuit elements, such as resistors and capacitors, so as to be reduced in size and to make consumption of electric power small. Accordingly, it is impossible to entirely substitute a digital signal processing technique for an analog signal processing technique unless a single-chip digital processor, namely, a microprocessor is available to carry out a great deal of computation. As is well known in the art, an advent of such a microprocessor has enabled a great deal of computation at a high speed. Such a microprocessor has been used as a signal processor for processing the digital signals.
In an article described in IEEE Journal of Solid State Circuits, Vol. SC-16, No. 4 (August 1981), pages 372 to 376, a signal processor is disclosed by Takao Nishitani et al. The signal processor comprises a data memory for storing data in a plurality of memory addresses, respectively, and a read-only memory for storing predetermined coefficients. A calculation performing circuit is also included in the signal processor to perform a predetermined calculation a plurality of times on the stored data read from the data memory by using the coefficients read from the read-only memory. The calculation performing circuit comprises a bit-parallel multiplier and an arithmetic and logic unit (ALU), which are connected to each other in series. The data memory is accessed by a memory accessing circuit which comprises an up/down counter and/or a register. The read-only memory is similarly accessed by a coefficient accessing circuit which comprises an up/down counter and/or a register.
Each of the up/down counters in the memory accessing circuit and the coefficient accessing circuit is effective to successively indicate stored data and the coefficients which are stored in successive addresses of the data memory and the read-only memory, respectively. In the signal processor, each of data is represented by two's complement of a binary number and is expressed by a fixed-point representation wherein a fixed point is placed between a most significant bit and a most significant bit but one. The most significant bit serves as a sign bit.
With this structure, the signal processor can be effectively used as the digital filter and, in particular, a finite impulse response (FIR) filter which carries out an arithmetic operation given by: ##EQU1## wherein x.sub.n and y.sub.n are representative of input and output data signals produced at a time instant n, respectively, and a.sub.i, coefficients. This is because the input data signals x.sub.n are stored in the successive addresses of the data memory and the coefficients a.sub.i are stored in successive addresses of the read-only memory.
On carrying out fast Fourier transform (FFT), the signal processor must process the zero-th through (N-1)-th input elements of an input data signal into the zeroth through (N-1)-th output elements of an output data signal, where N represents a predetermined positive integer. In the FFT, the stored data on which calculation should be performed are not always stored in the successive addresses of the data memory. The coefficients for the calculation are also not always stored in the successive addresses of the read-only memory. Therefore, complicated address indication must be carried out before performing the calculation.